Interrupts
Introduction
Processor
General considerations
The processor can interrupt the execution of the current process on 3 different event types :
- Exceptions/Faults : the running process made a fault, like the typical "General Protection Fault" when the process read or wrote memory in a forbidden place.
- Software interrupts : The process called an interrupt with the INT XX instruction.
- Hardware interrupts : Associated hardware raised the INT# line of the processor to inform it of any kind of event that just happened, like for a example "a key has been pressed".
The x86 family support 256 interrupts, and the first 32 are reserved for the exceptions and traps generated by the processor itself. All the others are available to software and external hardware.
Interrupt Descriptor Table (IDT)
The OS maintains an interrupt descriptor table used by the processor to know what to do when a specific interrupt is triggered. In real mode, it is just a list of FAR jump addresses located at physical memory address 0. In protected mode, it is a table of descriptors (interrupt gate, task gate...).
Once prepared, the interrupt descriptor table is set up using the LIDT instruction.
Hardware interrupts (IRQ)
Whenever the hardware wants to inform the system that something happened, like a new disc has been inserted or the user moved the mouse for example, it can deal with it in two ways :
- Update its internal status and wait for the operating system to check for it (this method is called polling).
- Request the interruption (IRQ) of the current process execution to immediately inform the operating system of a pending event.
Both methods have their own interest, but the thing to keep in mind is that interrupts are used to treat the event as quickly as possible. Interrupts are more resource consuming due to task switching and they reduce the control on how CPU time division between processes, but if the OS doesn't check as quickly as necessary the hardware status, it can possibly lose data (like for a high rate network card, the buffer can be full and overrun if the OS doesn't read it before next packets arrive).
The Programmable Interrupt Controller
As on most microcomputers, the x86 CPU have two external interrupt lines : a software maskable (SMI) and a non-maskable interrupt line (NMI). The SMI is used by standard hardware to trigger an interrupt, and the NMI is used during critical condition (memory or I/O parity error) or to force the OS to an escape routine.
To handle different interrupts, an programmable interrupt controller (PIC) is added. The PIC can handle multiple interrupt lines, priority between them, individual masking and so on. When an interrupt comes in, the INT# line is triggered and the interrupt number is sent to the CPU through data bus.
On the x86 family, the i8259 PIC was first used in the XT. It supported 8 differents IRQ. On the AT, an other i8259 was cascaded to the first one, leading up to 15 differents IRQs (16 minor the one used for cascading). It is only since some Pentium processors that it was replaced by an advanced PIC (APIC) supporting, amongst other things, 23 differents IRQ.