Intel x86 Architecture
Intel 8086
The Intel x86 architecture began in 1978 with the Intel 8086, a 16-bits processor. Typically clocked at a 4.77MHz frequency, it was able to natively handle 1MB of memory using a 20-bit address bus, with a 16-bit data bus (eventually an 8-bit data bus with the "low-cost" 8088). Memory was divided in 10 segments of RAM (640KB) whilst the 6 remaining segments were reserved for BIOS and ROMs (video, controllers, bundled BASIC...).
In the IBM PC, the processor was associated to an 8-bit external bus to manage I/O devices (later called ISA bus by competitors), and especially :
- an Intel 8259 programmable interrupt controller, which allowed up to 8 peripherals to interrupt the execution of the CPU to run a specific routine (called IRQ (Interrupt Request)), like echoing a letter when a key is pressed on a keyboard.
- an Intel 8253 programmable timer, clocked at 14.31818 MHz, provided timing functions, and audio speaker output.
- an Intel 8042 keyboard controller, which included also several specific system I/O.
- one or two Intel 8250 serial port controller (generally for mice, modem...)
- an Intel 8255 parallel port controller (generally for printers)
- a BIOS containing system bootup check and basic programming API.
You could also find a floppy disk controller, a hard disk controller on later XT models, a video card and ISA expansion slots to add new functionalities.
Widely introduced with the IBM PC in 1981 then PC/XT in 1983, clones were built on the same model leading to the IBM PC Compatible standard, using same or clones of the precited components.
Intel 80286
The next major step was with the introduction of the Intel 80286 in 1982, leading to the IBM PC/AT and subsequent PC/AT compatible computers. Generally clocked at 12MHz, the 80286 had a 24-bit memory address bus allowing it to address up to 16MB of memory. However, as the memory model introduced in the 8086 allowed only use of 16 segments of 64KB (1MB limit), a new operating mode called protected mode (opposed to real mode) was introduced.
The protected mode allows memory segments to be dynamically defined by the system by using segment selectors pointing to a table of descriptors. It also included the possibility to define levels of execution, differenciation between code and data, and between user-level and system-level.