Intel x86 Architecture - Revision history

Kindman at 14:35, 23 August 2012

2012-08-23T14:35:42Z

← Older revision		Revision as of 16:35, 23 August 2012
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	To solve the problem of configuration, the Plug & Play concept was introduced to allow the BIOS and/or the OS to configure dynamically the resources allocated to an ISA card, avoiding jumper configuration (so-called ''jumperless devices'').		To solve the problem of configuration, the Plug & Play concept was introduced to allow the BIOS and/or the OS to configure dynamically the resources allocated to an ISA card, avoiding jumper configuration (so-called ''jumperless devices'').

	Tentatives were made to introduce new buses : [http://en.wikipedia.org/wiki/~~EISA~~ EISA (Extended ISA)] performance was almost as poor as ISA and was not commonly used. IBM introduced the [http://en.wikipedia.org/wiki/~~MCA~~ MCA bus] in its PS/2 line, but the closed architecture led to competitors to design their own VLB (VESA local bus).		Tentatives were made to introduce new buses : [http://en.wikipedia.org/wiki/Extended_Industry_Standard_Architecture EISA (Extended ISA)] performance was almost as poor as ISA and was not commonly used. IBM introduced the [http://en.wikipedia.org/wiki/Micro_Channel_architecture MCA bus] in its PS/2 line, but the closed architecture led to competitors to design their own VLB (VESA local bus).

	The VLB bus allowed direct 32-bit transfers to memory at a 33MHz clock, so a theoritical bandwidth of 132MB/s, considerably increasing I/O performance. Another advantage of the VLB bus was to be pin-compatible with ISA, while adding an expansion connector for new features.		The VLB bus allowed direct 32-bit transfers to memory at a 33MHz clock, so a theoritical bandwidth of 132MB/s, considerably increasing I/O performance. Another advantage of the VLB bus was to be pin-compatible with ISA, while adding an expansion connector for new features.

Kindman at 14:34, 23 August 2012

2012-08-23T14:34:51Z

← Older revision		Revision as of 16:34, 23 August 2012
Line 42:		Line 42:
	To solve the problem of configuration, the Plug & Play concept was introduced to allow the BIOS and/or the OS to configure dynamically the resources allocated to an ISA card, avoiding jumper configuration (so-called ''jumperless devices'').		To solve the problem of configuration, the Plug & Play concept was introduced to allow the BIOS and/or the OS to configure dynamically the resources allocated to an ISA card, avoiding jumper configuration (so-called ''jumperless devices'').

	Tentatives were made to introduce new buses : [http://en.wikipedia.org/wiki/EISA\|EISA (Extended ISA)] performance was almost as poor as ISA and was not commonly used. IBM introduced the [http://en.wikipedia.org/wiki/MCA\|MCA bus] in its PS/2 line, but the closed architecture led to competitors to design their own VLB (VESA local bus).		Tentatives were made to introduce new buses : [http://en.wikipedia.org/wiki/EISA EISA (Extended ISA)] performance was almost as poor as ISA and was not commonly used. IBM introduced the [http://en.wikipedia.org/wiki/MCA MCA bus] in its PS/2 line, but the closed architecture led to competitors to design their own VLB (VESA local bus).

	The VLB bus allowed direct 32-bit transfers to memory at a 33MHz clock, so a theoritical bandwidth of 132MB/s, considerably increasing I/O performance. Another advantage of the VLB bus was to be pin-compatible with ISA, while adding an expansion connector for new features.		The VLB bus allowed direct 32-bit transfers to memory at a 33MHz clock, so a theoritical bandwidth of 132MB/s, considerably increasing I/O performance. Another advantage of the VLB bus was to be pin-compatible with ISA, while adding an expansion connector for new features.

Kindman at 14:34, 23 August 2012

2012-08-23T14:34:21Z

← Older revision		Revision as of 16:34, 23 August 2012
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	===Limits of ISA bus===		===Limits of ISA bus===
	Along with the x86 evolution were introduced a lot of ISA peripherals : audio card, modem cards, video cards, scanner adapters and so on. The ISA bus was limited to 8MHz with a constraint of 15 maximum IRQs and 7 DMA channels. On a typical motherboard, only 4 IRQs and 4 DMA channels were left for expansion cards; assignation of resources, including I/O ports, was done by setting jumpers directly on the card, leading to frequent resources conflicts and system hangs. Moreover, the 486 was clocked from 25MHz to 100MHz so ISA I/O latency was starting to be a real problem as bandwidth limit (theoritical ~~16Mb~~/s) didn't evolve.		Along with the x86 evolution were introduced a lot of ISA peripherals : audio card, modem cards, video cards, scanner adapters and so on. The ISA bus was limited to 8MHz with a constraint of 15 maximum IRQs and 7 DMA channels. On a typical motherboard, only 4 IRQs and 4 DMA channels were left for expansion cards; assignation of resources, including I/O ports, was done by setting jumpers directly on the card, leading to frequent resources conflicts and system hangs. Moreover, the 486 was clocked from 25MHz to 100MHz so ISA I/O latency was starting to be a real problem as bandwidth limit (theoritical 16MB/s) didn't evolve.

	===PnP ISA, EISA, MCA, VLB ~~and PCI~~ buses===		===PnP ISA, EISA, MCA, VLB buses===
	To solve the problem of configuration, the Plug & Play concept was introduced to allow the BIOS and/or the OS to configure dynamically the resources allocated to an ISA card, avoiding jumper configuration (so-called ''jumperless devices'').		To solve the problem of configuration, the Plug & Play concept was introduced to allow the BIOS and/or the OS to configure dynamically the resources allocated to an ISA card, avoiding jumper configuration (so-called ''jumperless devices'').

	Tentatives were made to introduce new buses : [http://en.wikipedia.org/wiki/EISA\|EISA (Extended ISA)] performance was almost as poor as ISA and was not commonly used. IBM introduced the [http://en.wikipedia.org/wiki/MCA\|MCA bus] in its PS/2 line, but the closed architecture led to competitors to design their own VLB (VESA local bus).		Tentatives were made to introduce new buses : [http://en.wikipedia.org/wiki/EISA\|EISA (Extended ISA)] performance was almost as poor as ISA and was not commonly used. IBM introduced the [http://en.wikipedia.org/wiki/MCA\|MCA bus] in its PS/2 line, but the closed architecture led to competitors to design their own VLB (VESA local bus).

	The VLB bus allowed direct 32-bit transfers to memory at a 33MHz clock, so a theoritical bandwidth of ~~132Mb~~/s, considerably increasing I/O performance.		The VLB bus allowed direct 32-bit transfers to memory at a 33MHz clock, so a theoritical bandwidth of 132MB/s, considerably increasing I/O performance. Another advantage of the VLB bus was to be pin-compatible with ISA, while adding an expansion connector for new features.

			==Intel Pentium==

			Both advantages of the ISA PnP and VLB bus were mixed into a new standard, called PCI. With the same performance of VLB, it included auto-configuration of resources, and a new compact slot.

Kindman: added 486 part

2012-08-23T14:29:03Z

added 486 part

← Older revision		Revision as of 16:29, 23 August 2012
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	==Intel 8086==		==Intel 8086==
	===Capabilities and memory model===		===Capabilities and memory model===
	The Intel x86 architecture began in 1978 with the i8086, a 16-bits processor. Typically clocked at a 4.77MHz frequency, it was able to natively handle 1MB of memory using a 20-bit address bus, with a 16-bit data bus (eventually an 8-bit data bus with the "low-cost" 8088). Memory was divided in 10 segments of RAM (640KB) whilst the 6 remaining segments were reserved for BIOS and ROMs (video, controllers, bundled BASIC...).		The Intel x86 architecture began in 1978 with the i8086, a 16-bits processor. Typically clocked at a 4.77MHz frequency, it was able to natively handle 1MB of memory using a 20-bit address bus, with a 16-bit data bus (eventually an 8-bit data bus with the "low-cost" 8088). Memory was divided in a total of 16 segments of 64KB : 10 segments of RAM (640KB) whilst the 6 remaining segments (384KB) were reserved for BIOS and ROMs (video, controllers, bundled BASIC...).

	===ISA bus and basic I/O components===		===ISA bus and basic I/O components===
Line 7:		Line 7:
	* an i8259 programmable interrupt controller, which allowed up to 8 peripherals to interrupt the execution of the CPU to run a specific routine (called ''IRQ (Interrupt Request)''), like echoing a letter when a key is pressed on a keyboard.		* an i8259 programmable interrupt controller, which allowed up to 8 peripherals to interrupt the execution of the CPU to run a specific routine (called ''IRQ (Interrupt Request)''), like echoing a letter when a key is pressed on a keyboard.
	* an i8253 programmable timer, clocked at 14.31818 MHz, which provided timing functions, and audio speaker output.		* an i8253 programmable timer, clocked at 14.31818 MHz, which provided timing functions, and audio speaker output.
	* an i8237 DMA controller, with 3 channels providing direct access between peripherals and memory, discharging the CPU of this task.		* an i8237 DMA controller, with 4 channels providing direct access between peripherals and memory, discharging the CPU of this task.
	* an i8042 keyboard controller, which also supported several specific system I/O functions.		* an i8042 keyboard controller, which also supported several specific system I/O functions.
	* one or two i8250 serial port controller (generally for mice, modem...)		* one or two i8250 serial port controller (generally for mice, modem...)
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	===I/O extensions===		===I/O extensions===
	* A new i8259 was cascaded to the first one, allowing up to 15 hardware IRQs to be sent to the CPU.		* A new i8259 PIC was cascaded to the first one, allowing up to 15 hardware IRQs to be sent to the CPU.
	* A new i8237 was cascaded to the first one, allowing up to 5 DMA channels to be used.		* A new i8237 DMA controller was cascaded to the first one, allowing up to 7 DMA channels to be used, the 3 new allowing 16-bit transfers.
	* As a consequence, the external ISA I/O bus was upgraded to a 16-bit data bus, allowing up to 64K I/O ports, 15 IRQs and 16M of addressable memory and the support of the 5 DMA channels.		* As a consequence, the external ISA I/O bus was upgraded to a 16-bit data bus, allowing up to 64K I/O ports, 15 IRQs and 16M of addressable memory and the support of the 7 DMA channels.

	==Intel 80386==		==Intel 80386==
	===Introducing 32-bit protected mode===		===Introducing 32-bit protected mode and virtual memory===
			The i80386 is probably the most important evolution in the x86 family. It is the first 32-bit processor of the family, and was still fully compatible with previous CPUs. Internal registers were enhanced to 32-bit, as was the address bus, being able to address 4GB of memory. On the "low-cost" 386SX and SL the data bus was painfully restrained to 16-bit, but also enhanced to 32-bit on other models.

			The protected mode also evolved to provide 32-bit segmentation and tasking, and added paging or so-called virtual memory. The concept of virtual memory is to build for each process its own view of memory : physical memory is divided in pages (typically 4KB each) and the OS build a page table translating the virtual address to a real physical address. The OS can then to isolate processes so they can't directly interfere between them, and also to protect the minimal interface with the OS, to avoid unwanted read/writes in the kernel code and data. This also permits the concept of swapping : when unused, a physical page can be transferred to hard disk; the page table is updated to tell the CPU that when this page will be accessed by the process, it will have to be read from disk, saving memory.

			==Intel 80486==

			===Limits of ISA bus===
			Along with the x86 evolution were introduced a lot of ISA peripherals : audio card, modem cards, video cards, scanner adapters and so on. The ISA bus was limited to 8MHz with a constraint of 15 maximum IRQs and 7 DMA channels. On a typical motherboard, only 4 IRQs and 4 DMA channels were left for expansion cards; assignation of resources, including I/O ports, was done by setting jumpers directly on the card, leading to frequent resources conflicts and system hangs. Moreover, the 486 was clocked from 25MHz to 100MHz so ISA I/O latency was starting to be a real problem as bandwidth limit (theoritical 16Mb/s) didn't evolve.

			===PnP ISA, EISA, MCA, VLB and PCI buses===
			To solve the problem of configuration, the Plug & Play concept was introduced to allow the BIOS and/or the OS to configure dynamically the resources allocated to an ISA card, avoiding jumper configuration (so-called ''jumperless devices'').

			Tentatives were made to introduce new buses : [http://en.wikipedia.org/wiki/EISA\|EISA (Extended ISA)] performance was almost as poor as ISA and was not commonly used. IBM introduced the [http://en.wikipedia.org/wiki/MCA\|MCA bus] in its PS/2 line, but the closed architecture led to competitors to design their own VLB (VESA local bus).

			The VLB bus allowed direct 32-bit transfers to memory at a 33MHz clock, so a theoritical bandwidth of 132Mb/s, considerably increasing I/O performance.

Kindman at 15:03, 22 August 2012

2012-08-22T15:03:13Z

← Older revision		Revision as of 17:03, 22 August 2012
Line 7:		Line 7:
	* an i8259 programmable interrupt controller, which allowed up to 8 peripherals to interrupt the execution of the CPU to run a specific routine (called ''IRQ (Interrupt Request)''), like echoing a letter when a key is pressed on a keyboard.		* an i8259 programmable interrupt controller, which allowed up to 8 peripherals to interrupt the execution of the CPU to run a specific routine (called ''IRQ (Interrupt Request)''), like echoing a letter when a key is pressed on a keyboard.
	* an i8253 programmable timer, clocked at 14.31818 MHz, which provided timing functions, and audio speaker output.		* an i8253 programmable timer, clocked at 14.31818 MHz, which provided timing functions, and audio speaker output.
			* an i8237 DMA controller, with 3 channels providing direct access between peripherals and memory, discharging the CPU of this task.
	* an i8042 keyboard controller, which also supported several specific system I/O functions.		* an i8042 keyboard controller, which also supported several specific system I/O functions.
	* one or two i8250 serial port controller (generally for mice, modem...)		* one or two i8250 serial port controller (generally for mice, modem...)
Line 20:		Line 21:

	===Protected mode===		===Protected mode===
	The protected mode allows memory segments to be dynamically defined by the system by using segment selectors pointing to a table of descriptors. It also included the possibility to define levels of execution, differenciation between code and data, ~~and~~ between user-level and system-level.		The protected mode allows memory segments to be dynamically defined by the system by using segment selectors pointing to a table of descriptors. It also included the possibility to define levels of execution, differenciation between code and data, between user-level and system-level, and multitasking.

	===I/O extensions===		===I/O extensions===
			* A new i8259 was cascaded to the first one, allowing up to 15 hardware IRQs to be sent to the CPU.
			* A new i8237 was cascaded to the first one, allowing up to 5 DMA channels to be used.
			* As a consequence, the external ISA I/O bus was upgraded to a 16-bit data bus, allowing up to 64K I/O ports, 15 IRQs and 16M of addressable memory and the support of the 5 DMA channels.

	==Intel 80386==		==Intel 80386==
	===Introducing 32-bit protected mode===		===Introducing 32-bit protected mode===

Kindman: Added titles

2012-08-22T14:53:23Z

Added titles

← Older revision		Revision as of 16:53, 22 August 2012
Line 1:		Line 1:
	==Intel 8086==		==Intel 8086==
	The Intel x86 architecture began in 1978 with the ~~Intel 8086~~, a 16-bits processor. Typically clocked at a 4.77MHz frequency, it was able to natively handle 1MB of memory using a 20-bit address bus, with a 16-bit data bus (eventually an 8-bit data bus with the "low-cost" 8088). Memory was divided in 10 segments of RAM (640KB) whilst the 6 remaining segments were reserved for BIOS and ROMs (video, controllers, bundled BASIC...).		===Capabilities and memory model===
			The Intel x86 architecture began in 1978 with the i8086, a 16-bits processor. Typically clocked at a 4.77MHz frequency, it was able to natively handle 1MB of memory using a 20-bit address bus, with a 16-bit data bus (eventually an 8-bit data bus with the "low-cost" 8088). Memory was divided in 10 segments of RAM (640KB) whilst the 6 remaining segments were reserved for BIOS and ROMs (video, controllers, bundled BASIC...).

			===ISA bus and basic I/O components===
	In the IBM PC, the processor was associated to an 8-bit external bus to manage I/O devices (later called '''ISA bus''' by competitors), and especially :		In the IBM PC, the processor was associated to an 8-bit external bus to manage I/O devices (later called '''ISA bus''' by competitors), and especially :
	* an ~~Intel 8259~~ programmable interrupt controller, which allowed up to 8 peripherals to interrupt the execution of the CPU to run a specific routine (called ''IRQ (Interrupt Request)''), like echoing a letter when a key is pressed on a keyboard.		* an i8259 programmable interrupt controller, which allowed up to 8 peripherals to interrupt the execution of the CPU to run a specific routine (called ''IRQ (Interrupt Request)''), like echoing a letter when a key is pressed on a keyboard.
	* an ~~Intel 8253~~ programmable timer, clocked at 14.31818 MHz, provided timing functions, and audio speaker output.		* an i8253 programmable timer, clocked at 14.31818 MHz, which provided timing functions, and audio speaker output.
	* an ~~Intel 8042~~ keyboard controller, which ~~included~~ also several specific system I/O.		* an i8042 keyboard controller, which also supported several specific system I/O functions.
	* one or two ~~Intel 8250~~ serial port controller (generally for mice, modem...)		* one or two i8250 serial port controller (generally for mice, modem...)
	* an ~~Intel 8255~~ parallel port controller (generally for printers)		* an i8255 parallel port controller (generally for printers)
	* a BIOS containing system bootup check and basic programming API.		* a BIOS containing system bootup check and basic programming API.
	You could also find a floppy disk controller, a hard disk controller on later XT models, a video card and ISA expansion slots to add new functionalities.		You could also find a floppy disk controller, a hard disk controller on later XT models, a video card and ISA expansion slots to add new functionalities.

	Widely introduced with the IBM PC in 1981 then PC/XT in 1983, clones were built on the same model leading to the ''IBM PC Compatible'' standard, ~~using~~ same ~~or clones of the precited~~ components.		Widely introduced with the IBM PC in 1981 then PC/XT in 1983, clones were built on the same model leading to the ''IBM PC Compatible'' standard, based on the same architecture and components.

	==Intel 80286==		==Intel 80286==
			===Capabilities and memory model===
	The next major step was with the introduction of the Intel 80286 in 1982, leading to the IBM PC/AT and subsequent ''PC/AT compatible'' computers. Generally clocked at 12MHz, the 80286 had a 24-bit memory address bus allowing it to address up to 16MB of memory. However, as the memory model introduced in the 8086 allowed only use of 16 segments of 64KB (1MB limit), a new operating mode called ''protected mode'' (opposed to ''real mode'') was introduced.		The next major step was with the introduction of the Intel 80286 in 1982, leading to the IBM PC/AT and subsequent ''PC/AT compatible'' computers. Generally clocked at 12MHz, the 80286 had a 24-bit memory address bus allowing it to address up to 16MB of memory. However, as the memory model introduced in the 8086 allowed only use of 16 segments of 64KB (1MB limit), a new operating mode called ''protected mode'' (opposed to ''real mode'') was introduced.

			===Protected mode===
	The protected mode allows memory segments to be dynamically defined by the system by using segment selectors pointing to a table of descriptors. It also included the possibility to define levels of execution, differenciation between code and data, and between user-level and system-level.		The protected mode allows memory segments to be dynamically defined by the system by using segment selectors pointing to a table of descriptors. It also included the possibility to define levels of execution, differenciation between code and data, and between user-level and system-level.

			===I/O extensions===


			==Intel 80386==
			===Introducing 32-bit protected mode===

Kindman at 14:48, 22 August 2012

2012-08-22T14:48:00Z

← Older revision		Revision as of 16:48, 22 August 2012
Line 2:		Line 2:
	The Intel x86 architecture began in 1978 with the Intel 8086, a 16-bits processor. Typically clocked at a 4.77MHz frequency, it was able to natively handle 1MB of memory using a 20-bit address bus, with a 16-bit data bus (eventually an 8-bit data bus with the "low-cost" 8088). Memory was divided in 10 segments of RAM (640KB) whilst the 6 remaining segments were reserved for BIOS and ROMs (video, controllers, bundled BASIC...).		The Intel x86 architecture began in 1978 with the Intel 8086, a 16-bits processor. Typically clocked at a 4.77MHz frequency, it was able to natively handle 1MB of memory using a 20-bit address bus, with a 16-bit data bus (eventually an 8-bit data bus with the "low-cost" 8088). Memory was divided in 10 segments of RAM (640KB) whilst the 6 remaining segments were reserved for BIOS and ROMs (video, controllers, bundled BASIC...).

	In the IBM PC, the processor was associated to an 8-bit external bus to manage I/O devices (later called '''ISA bus''' by competitors), and especially :		In the IBM PC, the processor was associated to an 8-bit external bus to manage I/O devices (later called '''ISA bus''' by competitors), and especially :
	* an Intel 8259 programmable interrupt controller, which allowed up to 8 peripherals to interrupt the execution of the CPU to run a specific routine (called ''IRQ (Interrupt Request)''), like echoing a letter when a key is pressed on a keyboard.		* an Intel 8259 programmable interrupt controller, which allowed up to 8 peripherals to interrupt the execution of the CPU to run a specific routine (called ''IRQ (Interrupt Request)''), like echoing a letter when a key is pressed on a keyboard.
	* an Intel 8253 programmable timer, clocked at 14.31818 MHz, provided timing functions, and audio speaker output.		* an Intel 8253 programmable timer, clocked at 14.31818 MHz, provided timing functions, and audio speaker output.

Kindman: Creation

2012-08-22T14:47:31Z

Creation

New page

==Intel 8086==
The Intel x86 architecture began in 1978 with the Intel 8086, a 16-bits processor. Typically clocked at a 4.77MHz frequency, it was able to natively handle 1MB of memory using a 20-bit address bus, with a 16-bit data bus (eventually an 8-bit data bus with the "low-cost" 8088). Memory was divided in 10 segments of RAM (640KB) whilst the 6 remaining segments were reserved for BIOS and ROMs (video, controllers, bundled BASIC...).

In the IBM PC, the processor was associated to an 8-bit external bus to manage I/O devices (later called '''ISA bus''' by competitors), and especially :
* an Intel 8259 programmable interrupt controller, which allowed up to 8 peripherals to interrupt the execution of the CPU to run a specific routine (called ''IRQ (Interrupt Request)''), like echoing a letter when a key is pressed on a keyboard.
* an Intel 8253 programmable timer, clocked at 14.31818 MHz, provided timing functions, and audio speaker output.
* an Intel 8042 keyboard controller, which included also several specific system I/O.
* one or two Intel 8250 serial port controller (generally for mice, modem...)
* an Intel 8255 parallel port controller (generally for printers)
* a BIOS containing system bootup check and basic programming API.
You could also find a floppy disk controller, a hard disk controller on later XT models, a video card and ISA expansion slots to add new functionalities.

Widely introduced with the IBM PC in 1981 then PC/XT in 1983, clones were built on the same model leading to the ''IBM PC Compatible'' standard, using same or clones of the precited components.

==Intel 80286==
The next major step was with the introduction of the Intel 80286 in 1982, leading to the IBM PC/AT and subsequent ''PC/AT compatible'' computers. Generally clocked at 12MHz, the 80286 had a 24-bit memory address bus allowing it to address up to 16MB of memory. However, as the memory model introduced in the 8086 allowed only use of 16 segments of 64KB (1MB limit), a new operating mode called ''protected mode'' (opposed to ''real mode'') was introduced.

The protected mode allows memory segments to be dynamically defined by the system by using segment selectors pointing to a table of descriptors. It also included the possibility to define levels of execution, differenciation between code and data, and between user-level and system-level.